1. Field of the Invention
The present invention relates to a method for fabricating the electrodes of a semiconductor capacitor, and more specifically, to a method for fabricating the electrodes of a stacked capacitor utilized in a dynamic random access memory (DRAM) cell.
2. Description of Related Art
Semiconductor capacitors have been widely utilized in semiconductor integrated circuit such as memory devices, oscillators, time-delay circuitry, and AD/DA converters. The elements of a semiconductor capacitor include two conducting layers and a dielectric therebetween. Therefore, the performance of the capacitor is determined by three physical characteristics: (1) the thickness of the dielectric layer, (2) the surface area of the conducting layers, and (3) electrical or mechanical properties of the dielectric and the conducting materials.
For a highly-integrated dynamic random access memory (DRAM), each cell dimension must be as small as possible to increase the device density. However, the electrode area of the capacitor in each memory cell should be large enough for data storage. Therefore, a three-dimensional stacked capacitor cell has been developed to satisfy the requirement. For example, a crown-type capacitor utilizes an upward extending electrode structure to increase the surface area. This structure therefore reduces soft-error rate (SER) and is compatible with dielectric materials of a high dielectric constant.
However, the complicated three-dimensional structure requires a lot of micro-lithography steps which increase the manufacturing cost of the memory device. For instance, the method disclosed in U.S. Pat. No. 5,278,091 utilizes two more masks to fabricate a stacked capacitor.
The method, referring to FIG. 1, uses a first additional micro-lithography step to define the space between two word lines 12. The space is provided for forming a poly plug 13 between the word lines 12. These word lines 12 are then isolated by a silicon nitride layer 14. The poly plug 13 and the silicon nitride layer 14 are then covered by a silicon dioxide layer 15.
Referring to FIG. 2, another additional micro-lithography step is carried out to define the silicon dioxide layer 15, thereby forming an opening 21 to the poly plug 13. Then a poly spacer 22 is formed in the opening 21 for subsequent steps of the electrode formation. Since the method requires two additional micro-lithography steps, the cost is increased.